1. Field of the Invention
The present invention relates to the field of non-volatile memorys, and more particularly, to a contactless channel write/erase flash memory cell/array and method of fabricating the same.
2. Description of the Prior Art
FIG. 1 is a cross-sectional view illustrating a conventional flash memory cell 10. FIG. 2 is a cross-section view illustrating a metal contact structure associated with the conventional flash memory cell structure. Referring to FIG. 1, the flash memory cell 10 is built upon a P-substrate 11 including a N-well 12 formed on the P-substrate 11 and a stacked gate 14 formed on the N-well 12. An N+-doped region 16 and an N+-doped region 18, functioning as a source and a drain of the flash memory cell 10, respectively, are formed two sides of the stacked gate 14 in the N-well 12 respectively. A P-doped region 20 is formed surrounding the N+-doped region 18 in the N-well 12 and a P-doped region 22 is formed beneath the stacked gate 14.
The stacked gate 14 includes a control gate 24 and a floating gate 26. A word line voltage VWL is applied to the control gate 24 for controlling the flash memory cell 10. The floating gate 26 is in a “floating” state without any direct connection with external circuits for storing charges. A source voltage VSL is applied to the N+-doped region 16 (source terminal), and a drain voltage VBL is applied to the N+-doped region 18 (drain terminal).
With these applied voltages, electrons (e−) eject from the floating gate 26 to the N+-doped region 18 due to the edge Fowler-Nordheim effect and the flash memory cell 10 is programmed. However, upon applying a voltage on the drain terminal, an undesirable depletion region outside the N+-doped region 18 is also produced. Furthermore, hot holes (e+) will be generated leading to hot hole injection in the presence of lateral electric field. These hot holes can severely affect the normal operation of a flash memory cell 10. With a short-circuiting connection between the N+-doped region 18 of the drain terminal and the P-doped region 20, the above-mentioned problems can be prevented. Referring to FIG. 2, a metal contact 30 penetrates through an N+-doped region 32 of each drain terminal and into a P-doped region 34. A bit line voltage VBL is applied to the N+-doped region 32 of each drain terminal through the metal contact 30 so that the N+-doped region 32 and the P-doped region 34 are short-circuited together.
In addition, a predetermined distance 38 between the metal contact 30 and the stacked gate 36 has to be maintained in the conventional flash memory cell for preventing interferences caused by each other. However, increasing cell density is constantly in demand in current market, and such conventional flash memory cell design apparently can not satisfy such demand.